1. Field of the Invention
The present invention generally relates to PLL (Phase-Locked Loop) circuits, and more particularly to a PLL circuit which generates a clock signal synchronized with data signal serially transferred and signal processing such as a PLL circuit.
Generally, data is serially transmitted over a single transmission line. In order to receive a data signal serially transmitted, it is necessary to generate a clock signal which is synchronized with the data signal, more specifically, which has a frequency and phase coinciding with those of the received data signal.
2. Description of the Prior Art
FIG. 1 is a block diagram of a configuration which generates a clock signal from a serial data signal serially transmitted and synchronized with the received serial data signal. A frequency extracting unit 10 extracts a frequency component of the clock signal from a serial input data signal Ds in which data "0" and "1" occur irregularly. A SAW (Surface Acoustic Wave) filter 12 filters the frequency component of the clock signal, and generates therefrom the clock signal synchronized with the input data signal Ds.
FIG. 2 is a block diagram of another configuration using a PLL circuit. Generally, the PLL circuit is capable of generating a clock signal from a certain clock signal, the former clock signal being synchronized with the latter clock signal and having a frequency equal to that of the latter clock signal or an integer multiple of the frequency of the latter clock signal. Recently, there has been considerable activity in applications of the configuration shown in FIG. 2 rather than the configuration shown in FIG. 1. The configuration shown in FIG. 2 is an application of the PLL circuit directed to generate the clock signal from the serial input data signal. The PLL circuit shown in FIG. 2 includes a phase comparator 20, a loop filter 30, a voltage controlled oscillator (VCO) 40 and a frequency divider 50. The phase comparator 20 compares the phase of the serial input data signal Ds with that of a clock signal CLK, and outputs a signal dependent on the phase difference. The loop filter 30 integrates the signal indicating the phase difference, and generates a control voltage Vc therefrom. The control voltage Vc is output to the VCO 40, which oscillates at a frequency Vc defined by the control voltage Vc. The frequency divider 50 divides the oscillation frequency and thereby outputs the clock signal CLK.
As shown in FIG. 2, the phase comparator 20 is made up of a delay circuit D, an OR circuit (gate) OR1, and NOR circuits (gates) NOR1 and NOR2.
FIG. 3 is a timing chart of the operation of the PLL circuit shown in FIG. 2. In FIG. 3, symbols N1 through N6 respectively denote signals at nodes N1 through N6 shown in FIG. 2. Further, the expressions shown in the parentheses indicate the logical expressions showing the corresponding gate circuits. For example, the phrase "N3 (=N1+/N2: where symbol "/" denotes bar indicative of the inverted version of the signal (N2 in this example))" denotes the output signal of the OR gate OR1, and means the result of the OR operation on the signal N1 (input data signal Ds) and the inverted version of the signal N2 delayed by the delay circuit D.
The OR circuit OR1 defines, each falling edge of the input data signal Ds, a compare window (the period during which the signal N3 is low) used to compare the phase of the clock signal CLK and the phase of the input data signal Ds. The NOR circuits NOR1 and NOR2 perform the NOR operation on the compare window signal (low level) N3 and the clock signal CLK, and respectively generate an f.sub.up signal (leading pulse signal) N5 and an f.sub.down signal (a lagging pulse signal) N6. These signals N5 and N6 are applied to corresponding terminals of the loop filter 30, which separately integrates the f.sub.up signal N5 and the f.sub.down signal N6, and outputs the result of the above integration to the VCO 40. When the value of the integration of the f.sub.up signal N5 is greater than that of the integration of the f.sub.down signal N6, the loop filter 40 outputs the control voltage Vc which increases the oscillation frequency of the VCO 40. When the value of the integration of the f.sub.up signal N5 is less than that of the integration of the f.sub.down signal N6, the loop filter 40 outputs the control voltage Vc which decreases the oscillation frequency of the VCO 40.
In the case shown in FIG. 3, the sum of the pulse widths of the f.sub.up signal N5 in cycles P1 through P6 is greater than that of the pulse widths of the f.sub.down signal N6 in the same cycles as mentioned above. Hence, the loop filter 30 generates the control voltage Vc which functions to increase the oscillation frequency of the VCO 40. Hence, the oscillation frequency becomes higher and the PLL circuit is operationally locked when the sum of the pulse widths of the f.sub.up signal N5 becomes equal to that of the pulse widths of the f.sub.down signal N6. That is, the PLL circuit is locked when the phase of the rising edge of the clock signal CLK coincides with the center of the compare window N3.
In general, the frequency component of the clock signal generated from the input data signal Ds is twice the frequency (data transmission rate) of the data signal. Even in the example shown in FIG. 3, the frequency of the clock signal CLK is set to be twice the frequency of the data signal. With the above setting of the frequency of the clock signal CLK, it is possible to ensure that the rising edge of the clock signal CLK is present within the compare window N3 without exception.
However, the PLL circuit shown in FIG. 2 has the following disadvantages.
First, the PLL circuit is suitable for applications in which a clock signal is processed as an input signal in which binary values "0" and "1" repeatedly appear regularly. However, the PLL circuit is not suitable for a data signal in which binary values "0" and "1" appear irregularly. More particularly, in the example shown in FIG. 3, the phase comparison is performed in the cycles P1, P3 and P6. The nature of the data signal allows the input data signal Ds to be fixed to "0" or "1" for a long time. During this time, the compare window N3 cannot be generated and the phase comparing operation cannot be executed. As a result, it is impossible to control the VCO 40 during the above time period and compensate for variations in the environment such as variations in the temperature and the power supply voltage. When the next data is received, there may be large deviations in the oscillation frequency and phase of the clock signal, and it will take a long time for the PLL circuit to be operationally locked. It is thus concluded that the PLL circuit shown in FIG. 2 is applicable only to a limited communication in which data is not frequently interrupted.
Second, as has been described previously, the clock signal CLK for use in phase comparison is needed to have a frequency equal to twice the frequency of the data signal. Recently, there has been considerable activity in improving data transmission rate in order to transmit a large amount of data at high speeds. As the transmission rate becomes higher, the frequency of the clock signal equal to twice the transmission rate becomes higher. However, as the frequency of the clock signal becomes higher, a larger amount of energy is consumed, and the crosstalk becomes larger when transferring signals on a printed circuit board. From the above viewpoints, it is desirable to provide a PLL circuit capable of performing the phase comparing operation using a clock signal having a frequency equal to that of the data signal. However, as will be described in detail below, a problem will occur in which it is no longer ensured that the rising edge of the clock signal CLK is present within the compare window N3 without exception. The above problem will be described below in conjunction with FIG. 4.
FIG. 4 is a timing chart of an operation in which the frequency of the clock signal CLK (N4) is set equal to that of the input data signal Ds. In the cycles P1 and P3, the pulse width of the f.sub.up signal is greater than that of the f.sub.down signal, and thus the VCO 40 is operated so that its oscillation frequency becomes high. However, in the cycle P6, the pulse width of the f.sub.down signal N6 is greater than that of the f.sub.up signal N5, and thus the VCO 40 is reversely operated so that its oscillation frequency becomes low. In other words, when the falling edge of the clock signal CLK is present within the compare window N3, the reverse relationship between the f.sub.up signal N5 and the f.sub.down signal N6 occurs, and the loop filter 30 is notified of the above reverse relationship. Hence, it is impossible to lock the PLL circuit in synchronism with the phase of the input data signal Ds.